/*
 * registers.h - MFD REGISTERS H for SC2705
 * Copyright (c) 2017 Dialog Semiconductor.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __SC2705_REGISTERS_H
#define __SC2705_REGISTERS_H

#ifndef BIT
#define BIT(x) (1 << (x))
#endif


/* Registers */
#define SC2705_STATUS_A			0x00
#define SC2705_STATUS_B			0x01
#define SC2705_STATUS_C			0x02
#define SC2705_STATUS_D			0x03
#define SC2705_STATUS_E			0x04
#define SC2705_STATUS_F			0x05
#define SC2705_STATUS_G			0x06
#define SC2705_STATUS_H			0x07
#define SC2705_STATUS_I			0x08
#define SC2705_EVENT_A			0x09
#define SC2705_EVENT_B			0x0A
#define SC2705_EVENT_C			0x0B
#define SC2705_EVENT_D			0x0C
#define SC2705_EVENT_E			0x0D
#define SC2705_EVENT_F			0x0E
#define SC2705_EVENT_G			0x0F
#define SC2705_EVENT_H			0x10
#define SC2705_EVENT_I			0x11
#define SC2705_MASK_A			0x12
#define SC2705_MASK_B			0x13
#define SC2705_MASK_C			0x14
#define SC2705_MASK_D			0x15
#define SC2705_MASK_E			0x16
#define SC2705_MASK_F			0x17
#define SC2705_MASK_G			0x18
#define SC2705_MASK_H			0x19
#define SC2705_MASK_I			0x1A
#define SC2705_VIN_CTRL_A		0x1B
#define SC2705_VBAT_CTRL_A		0x1C
#define SC2705_DCDC_CTRL_A		0x1D
#define SC2705_DCDC_CTRL_B		0x1E
#define SC2705_DCDC_CTRL_C		0x1F
#define SC2705_DCDC_CTRL_D		0x20
#define SC2705_DCDC_CTRL_E		0x21
#define SC2705_DCDC_CTRL_F		0x22
#define SC2705_CHG_CTRL_A		0x23
#define SC2705_CHG_CTRL_B		0x24
#define SC2705_CHG_CTRL_C		0x25
#define SC2705_CHG_CTRL_D		0x26
#define SC2705_CHG_CTRL_E		0x27
#define SC2705_BATSW_CTRL_A	0x28
#define SC2705_TBAT_CTRL_A		0x29
#define SC2705_TJUNC_CTRL_A		0x2A
#define SC2705_ADC_CTRL_A		0x2B
#define SC2705_ADC_RES_0		0x2C
#define SC2705_ADC_RES_1		0x2D
#define SC2705_ADC_RES_2		0x2E
#define SC2705_ADC_RES_3		0x2F
#define SC2705_ADC_RES_4		0x30
#define SC2705_ADC_RES_5		0x31
#define SC2705_GPIO_CONF_A		0x32
#define SC2705_GPIO_CONF_B		0x33
#define SC2705_TWI_CTRL_A		0x34
#define SC2705_TWI_CTRL_B		0x35
#define SC2705_CHG_TIMER_CTRL_A	0x36
#define SC2705_CHG_TIMER_CTRL_B	0x37
#define SC2705_CHG_TIMER_CTRL_C	0x38
#define SC2705_CONF_A			0x40
#define SC2705_CONF_B			0x41

/* SC2705_STATUS_A = 0x00 */
#define SC2705_S_ADP_DET_SHIFT		0
#define SC2705_S_ADP_DET_MASK		BIT(0)
#define SC2705_S_VIN2BAT_SHIFT		1
#define SC2705_S_VIN2BAT_MASK		BIT(1)
#define SC2705_S_VIN_UV_SHIFT		2
#define SC2705_S_VIN_UV_MASK		BIT(2)
#define SC2705_S_VIN_DROP_SHIFT		3
#define SC2705_S_VIN_DROP_MASK		BIT(3)
#define SC2705_S_VIN_OV_SHIFT		4
#define SC2705_S_VIN_OV_MASK		BIT(4)
#define SC2705_S_VBAT_UV_SHIFT		5
#define SC2705_S_VBAT_UV_MASK		BIT(5)
#define SC2705_S_VBAT_OV_SHIFT		6
#define SC2705_S_VBAT_OV_MASK		BIT(6)

/* SC2705_STATUS_B = 0x01 */
#define SC2705_S_TJUNC_WARN_SHIFT	0
#define SC2705_S_TJUNC_WARN_MASK	BIT(0)
#define SC2705_S_TJUNC_CRIT_SHIFT	1
#define SC2705_S_TJUNC_CRIT_MASK	BIT(1)
#define SC2705_S_TBAT_T1_SHIFT		3
#define SC2705_S_TBAT_T1_MASK		BIT(3)
#define SC2705_S_TBAT_T2_SHIFT		4
#define SC2705_S_TBAT_T2_MASK		BIT(4)
#define SC2705_S_TBAT_T3_SHIFT		5
#define SC2705_S_TBAT_T3_MASK		BIT(5)
#define SC2705_S_TBAT_T4_SHIFT		6
#define SC2705_S_TBAT_T4_MASK		BIT(6)
#define SC2705_S_BATDET_SHIFT		7
#define SC2705_S_BATDET_MASK		BIT(7)

/* SC2705_STATUS_C = 0x02 */
#define SC2705_S_VIN_REV_SHORT_SHIFT	0
#define SC2705_S_VIN_REV_SHORT_MASK	BIT(0)
#define SC2705_S_VIN_REV_OV_SHIFT	1
#define SC2705_S_VIN_REV_OV_MASK	BIT(1)
#define SC2705_S_IIN_REV_LIM_SHIFT	3
#define SC2705_S_IIN_REV_LIM_MASK	BIT(3)
#define SC2705_S_LOWBAT_SHIFT		5
#define SC2705_S_LOWBAT_MASK		BIT(5)
#define SC2705_S_IIN_LIM_SHIFT		7
#define SC2705_S_IIN_LIM_MASK		BIT(7)

/* SC2705_STATUS_D = 0x03 */
#define SC2705_S_CHG_STAT_SHIFT		0
#define SC2705_S_CHG_STAT_MASK		(0x7 << 0)
#define SC2705_S_CHG_STAT_DCDC_OFF	(0x0 << 0)
#define SC2705_S_CHG_STAT_PRE		(0x1 << 0)
#define SC2705_S_CHG_STAT_CC		(0x2 << 0)
#define SC2705_S_CHG_STAT_CV		(0x3 << 0)
#define SC2705_S_CHG_STAT_TOP_OFF	(0x4 << 0)
#define SC2705_S_CHG_STAT_FULL		(0x5 << 0)
#define SC2705_S_CHG_STAT_FAULT_L1	(0x6 << 0)
#define SC2705_S_CHG_STAT_FAULT_L2	(0x7 << 0)
#define SC2705_S_VSYS_OV_SHIFT		4
#define SC2705_S_VSYS_OV_MASK		BIT(4)

/* SC2705_STATUS_E = 0x04 */
#define SC2705_S_GPI0_SHIFT		0
#define SC2705_S_GPI0_MASK		BIT(0)
#define SC2705_S_GPI1_SHIFT		1
#define SC2705_S_GPI1_MASK		BIT(1)
#define SC2705_S_GPI2_SHIFT		2
#define SC2705_S_GPI2_MASK		BIT(2)
#define SC2705_S_GPI3_SHIFT		3
#define SC2705_S_GPI3_MASK		BIT(4)
#define SC2705_S_VSYS_UV_SHIFT	4
#define SC2705_S_VSYS_UV_MASK	BIT(4)
#define SC2705_S_BOOST_STARTUP_OV_SHIFT		5
#define SC2705_S_BOOST_STARTUP_OV_MASK		BIT(5)
#define SC2705_S_FLASH_LDO_SHORT_CKT_SHIFT	6
#define SC2705_S_FLASH_LDO_SHORT_CKT_MASK	BIT(6)
#define SC2705_S_IDLE_LP_SHIFT		7
#define SC2705_S_IDLE_LP_MASK		BIT(7)

/* SC2705_STATUS_G = 0x06 */
#define SC2705_S_IIN_LIM_EFF_SHIFT	0
#define SC2705_S_IIN_LIM_EFF_MASK	(0xFF << 0)

/* SC2705_STATUS_H = 0x07 */
#define SC2705_S_IBAT_CHG_EFF_SHIFT	0
#define SC2705_S_IBAT_CHG_EFF_MASK	(0xFF << 0)

/* SC2705_STATUS_I = 0x08 */
#define SC2705_S_VBAT_CHG_EFF_SHIFT	0
#define SC2705_S_VBAT_CHG_EFF_MASK	(0xFF << 0)

/* SC2705_EVENT_A = 0x09 */
#define SC2705_E_ADP_DET_SHIFT		0
#define SC2705_E_ADP_DET_MASK		BIT(0)
#define SC2705_E_VIN2BAT_SHIFT		1
#define SC2705_E_VIN2BAT_MASK		BIT(1)
#define SC2705_E_VIN_UV_SHIFT		2
#define SC2705_E_VIN_UV_MASK		BIT(2)
#define SC2705_E_VIN_DROP_SHIFT		3
#define SC2705_E_VIN_DROP_MASK		BIT(3)
#define SC2705_E_VIN_OV_SHIFT		4
#define SC2705_E_VIN_OV_MASK		BIT(4)
#define SC2705_E_VBAT_UV_SHIFT		5
#define SC2705_E_VBAT_UV_MASK		BIT(5)
#define SC2705_E_VBAT_OV_SHIFT		6
#define SC2705_E_VBAT_OV_MASK		BIT(6)
#define SC2705_E_IN_PWR_BLOCK_SHIFT	7
#define SC2705_E_IN_PWR_BLOCK_MASK	BIT(7)

/* SC2705_EVENT_B = 0x0A */
#define SC2705_E_TJUNC_WARN_SHIFT	0
#define SC2705_E_TJUNC_WARN_MASK	BIT(0)
#define SC2705_E_TJUNC_CRIT_SHIFT	1
#define SC2705_E_TJUNC_CRIT_MASK	BIT(1)
#define SC2705_E_TJUNC_POR_SHIFT	2
#define SC2705_E_TJUNC_POR_MASK		BIT(2)
#define SC2705_E_TBAT_T1_SHIFT		3
#define SC2705_E_TBAT_T1_MASK		BIT(3)
#define SC2705_E_TBAT_T2_SHIFT		4
#define SC2705_E_TBAT_T2_MASK		BIT(4)
#define SC2705_E_TBAT_T3_SHIFT		5
#define SC2705_E_TBAT_T3_MASK		BIT(5)
#define SC2705_E_TBAT_T4_SHIFT		6
#define SC2705_E_TBAT_T4_MASK		BIT(6)
#define SC2705_E_BATDET_SHIFT		7
#define SC2705_E_BATDET_MASK		BIT(7)

/* SC2705_EVENT_C = 0x0B */
#define SC2705_E_VIN_REV_SHORT_SHIFT		0
#define SC2705_E_VIN_REV_SHORT_MASK		BIT(0)
#define SC2705_E_VIN_REV_OV_SHIFT		1
#define SC2705_E_VIN_REV_OV_MASK		BIT(1)
#define SC2705_E_DCDC_REV_BOOST_FAULT_SHIFT	2
#define SC2705_E_DCDC_REV_BOOST_FAULT_MASK	BIT(2)
#define SC2705_E_IIN_REV_LIM_SHIFT		3
#define SC2705_E_IIN_REV_LIM_MASK		BIT(3)
#define SC2705_E_IIN_REV_LIM_MAX_SHIFT		4
#define SC2705_E_IIN_REV_LIM_MAX_MASK		BIT(4)
#define SC2705_E_LOWBAT_SHIFT			5
#define SC2705_E_LOWBAT_MASK			BIT(5)
#define SC2705_E_ADC_DONE_SHIFT			6
#define SC2705_E_ADC_DONE_MASK			BIT(6)
#define SC2705_E_IIN_LIM_SHIFT			7
#define SC2705_E_IIN_LIM_MASK			BIT(7)

/* SC2705_EVENT_D = 0x0C */
#define SC2705_E_CHG_STAT_SHIFT		0
#define SC2705_E_CHG_STAT_MASK		BIT(0)
#define SC2705_E_VSYS_POR_SHIFT		3
#define SC2705_E_VSYS_POR_MASK		BIT(3)
#define SC2705_E_VSYS_OV_SHIFT		4
#define SC2705_E_VSYS_OV_MASK		BIT(4)
#define SC2705_E_WD_SHIFT		5
#define SC2705_E_WD_MASK		BIT(5)
#define SC2705_E_TIMEOUT_PRE_SHIFT	6
#define SC2705_E_TIMEOUT_PRE_MASK	BIT(6)
#define SC2705_E_TIMEOUT_CCCV_SHIFT	7
#define SC2705_E_TIMEOUT_CCCV_MASK	BIT(7)

/* SC2705_EVENT_E = 0x0D */
#define SC2705_E_GPI0_SHIFT		0
#define SC2705_E_GPI0_MASK		BIT(0)
#define SC2705_E_GPI1_SHIFT		1
#define SC2705_E_GPI1_MASK		BIT(1)
#define SC2705_E_GPI2_SHIFT		2
#define SC2705_E_GPI2_MASK		BIT(2)
#define SC2705_E_GPI3_SHIFT		3
#define SC2705_E_GPI3_MASK		BIT(4)
#define SC2705_E_VSYS_UV_SHIFT	4
#define SC2705_E_VSYS_UV_MASK	BIT(4)
#define SC2705_E_BOOST_STARTUP_OV_SHIFT		5
#define SC2705_E_BOOST_STARTUP_OV_MASK		BIT(5)
#define SC2705_E_FLASH_LDO_SHORT_CKT_SHIFT	6
#define SC2705_E_FLASH_LDO_SHORT_CKT_MASK	BIT(6)

/* SC2705_EVENT_F = 0x0E */
#define SC2705_E_TORCH_CHG_OV_SHIFT	0
#define SC2705_E_TORCH_CHG_OV_MASK	BIT(0)

/* SC2705_MASK_A = 0x12 */
#define SC2705_M_ADP_DET_SHIFT		0
#define SC2705_M_ADP_DET_MASK		BIT(0)
#define SC2705_M_VIN2BAT_SHIFT		1
#define SC2705_M_VIN2BAT_MASK		BIT(1)
#define SC2705_M_VIN_UV_SHIFT		2
#define SC2705_M_VIN_UV_MASK		BIT(2)
#define SC2705_M_VIN_DROP_SHIFT		3
#define SC2705_M_VIN_DROP_MASK		BIT(3)
#define SC2705_M_VIN_OV_SHIFT		4
#define SC2705_M_VIN_OV_MASK		BIT(4)
#define SC2705_M_VBAT_UV_SHIFT		5
#define SC2705_M_VBAT_UV_MASK		BIT(5)
#define SC2705_M_VBAT_OV_SHIFT		6
#define SC2705_M_VBAT_OV_MASK		BIT(6)
#define SC2705_M_IN_PWR_BLOCK_SHIFT	7
#define SC2705_M_IN_PWR_BLOCK_MASK	BIT(7)

/* SC2705_MASK_B = 0x13 */
#define SC2705_M_TJUNC_WARN_SHIFT	0
#define SC2705_M_TJUNC_WARN_MASK	BIT(0)
#define SC2705_M_TJUNC_CRIT_SHIFT	1
#define SC2705_M_TJUNC_CRIT_MASK	BIT(1)
#define SC2705_M_TJUNC_POR_SHIFT	2
#define SC2705_M_TJUNC_POR_MASK		BIT(2)
#define SC2705_M_TBAT_T1_SHIFT		3
#define SC2705_M_TBAT_T1_MASK		BIT(3)
#define SC2705_M_TBAT_T2_SHIFT		4
#define SC2705_M_TBAT_T2_MASK		BIT(4)
#define SC2705_M_TBAT_T3_SHIFT		5
#define SC2705_M_TBAT_T3_MASK		BIT(5)
#define SC2705_M_TBAT_T4_SHIFT		6
#define SC2705_M_TBAT_T4_MASK		BIT(6)
#define SC2705_M_BATDET_SHIFT		7
#define SC2705_M_BATDET_MASK		BIT(7)

/* SC2705_MASK_C = 0x14 */
#define SC2705_M_VIN_REV_SHORT_SHIFT		0
#define SC2705_M_VIN_REV_SHORT_MASK		BIT(0)
#define SC2705_M_VIN_REV_OV_SHIFT		1
#define SC2705_M_VIN_REV_OV_MASK		BIT(1)
#define SC2705_M_DCDC_REV_BOOST_FAULT_SHIFT	2
#define SC2705_M_DCDC_REV_BOOST_FAULT_MASK	BIT(2)
#define SC2705_M_IIN_REV_LIM_SHIFT		3
#define SC2705_M_IIN_REV_LIM_MASK		BIT(3)
#define SC2705_M_IIN_REV_LIM_MAX_SHIFT		4
#define SC2705_M_IIN_REV_LIM_MAX_MASK		BIT(4)
#define SC2705_M_LOWBAT_SHIFT			5
#define SC2705_M_LOWBAT_MASK			BIT(5)
#define SC2705_M_ADC_DONE_SHIFT			6
#define SC2705_M_ADC_DONE_MASK			BIT(6)
#define SC2705_M_IIN_LIM_SHIFT			7
#define SC2705_M_IIN_LIM_MASK			BIT(7)

/* SC2705_MASK_D = 0x15 */
#define SC2705_M_CHG_STAT_SHIFT		0
#define SC2705_M_CHG_STAT_MASK		BIT(0)
#define SC2705_M_VSYS_POR_SHIFT		3
#define SC2705_M_VSYS_POR_MASK		BIT(3)
#define SC2705_M_VSYS_OV_SHIFT		4
#define SC2705_M_VSYS_OV_MASK		BIT(4)
#define SC2705_M_WD_SHIFT		5
#define SC2705_M_WD_MASK		BIT(5)
#define SC2705_M_TIMEOUT_PRE_SHIFT	6
#define SC2705_M_TIMEOUT_PRE_MASK	BIT(6)
#define SC2705_M_TIMEOUT_CCCV_SHIFT	7
#define SC2705_M_TIMEOUT_CCCV_MASK	BIT(7)

/* SC2705_MASK_E = 0x16 */
#define SC2705_M_GPI0_SHIFT		0
#define SC2705_M_GPI0_MASK		BIT(0)
#define SC2705_M_GPI1_SHIFT		1
#define SC2705_M_GPI1_MASK		BIT(1)
#define SC2705_M_GPI2_SHIFT		2
#define SC2705_M_GPI2_MASK		BIT(2)
#define SC2705_M_GPI3_SHIFT		3
#define SC2705_M_GPI3_MASK		BIT(3)
#define SC2705_M_VSYS_UV_SHIFT	4
#define SC2705_M_VSYS_UV_MASK	BIT(4)
#define SC2705_M_BOOST_STARTUP_OV_SHIFT		5
#define SC2705_M_BOOST_STARTUP_OV_MASK		BIT(5)
#define SC2705_M_FLASH_LDO_SHORT_CKT_SHIFT	6
#define SC2705_M_FLASH_LDO_SHORT_CKT_MASK	BIT(6)

/* SC2705_MASK_F = 0x17 */
#define SC2705_M_TORCH_CHG_OV_SHIFT		0
#define SC2705_M_TORCH_CHG_OV_MASK		BIT(0)

/* SC2705_VIN_CTRL_A = 0x1B */
#define SC2705_VIN_DROP_SHIFT		0
#define SC2705_VIN_DROP_MASK		(0xFF << 0)

/* SC2705_VBAT_CTRL_A = 0x1C */
#define SC2705_VBAT_UV_SHIFT		0
#define SC2705_VBAT_UV_MASK		(0xF << 0)
#define SC2705_VBAT_OV_SHIFT		4
#define SC2705_VBAT_OV_MASK		(0xF << 4)

/* SC2705_DCDC_CTRL_A = 0x1D */
#define SC2705_CHG_EN_SHIFT		0
#define SC2705_CHG_EN_MASK		BIT(0)
#define SC2705_DCDC_EN_SHIFT		1
#define SC2705_DCDC_EN_MASK		BIT(1)
#define SC2705_OTG_EN_SHIFT			2
#define SC2705_OTG_EN_MASK			BIT(2)
#define SC2705_DCDC_FSW_AUTO_SHIFT	3
#define SC2705_DCDC_FSW_AUTO_MASK	BIT(3)
#define SC2705_DCDC_FSW_SHIFT		4
#define SC2705_DCDC_FSW_MASK		(0x3 << 4)
#define SC2705_TORCH_CHG_SHIFT		6
#define SC2705_TORCH_CHG_MASK		BIT(6)
#define SC2705_FLASH_EN_SHIFT		7
#define SC2705_FLASH_EN_MASK		BIT(7)

/* SC2705_DCDC_CTRL_B = 0x1E */
#define SC2705_DCDC_PEAK_ILIM_SHIFT		0
#define SC2705_DCDC_PEAK_ILIM_MASK		(0x3 << 0)
#define SC2705_IIN_REV_LIM_SHIFT		4
#define SC2705_IIN_REV_LIM_MASK			(0x7 << 4)
#define SC2705_IN_PWR_RED_SHIFT			7
#define SC2705_IN_PWR_RED_MASK			BIT(7)

/* SC2705_DCDC_CTRL_C = 0x1F */
#define SC2705_IIN_LIM_SEL_SHIFT		0
#define SC2705_IIN_LIM_SEL_MASK			BIT(0)
#define SC2705_IIN_LIM_ISET_SHIFT		1
#define SC2705_IIN_LIM_ISET_MASK		BIT(1)
#define SC2705_DCDC_REV_BOOST_FSW_SHIFT		2
#define SC2705_DCDC_REV_BOOST_FSW_MASK		(0x3 << 2)
#define SC2705_IIN_LIM_SLEW_SHIFT		4
#define SC2705_IIN_LIM_SLEW_MASK		(0x3 << 4)
#define SC2705_T_REV_ILIM_MAX_SHIFT		6
#define SC2705_T_REV_ILIM_MAX_MASK		(0x3 << 6)

/* SC2705_DCDC_CTRL_D = 0x20 */
#define SC2705_IIN_LIM0_SHIFT		0
#define SC2705_IIN_LIM0_MASK		(0x7 << 0)
#define SC2705_IIN_LIM1_SHIFT		4
#define SC2705_IIN_LIM1_MASK		(0x7 << 4)

/* SC2705_DCDC_CTRL_E = 0x21 */
#define SC2705_IIN_DROP_INTERVAL_SHIFT	0
#define SC2705_IIN_DROP_INTERVAL_MASK	(0x3 << 0)
#define SC2705_IIN_DROP_AMOUNT_SHIFT	2
#define SC2705_IIN_DROP_AMOUNT_MASK	(0x3 << 2)
#define SC2705_VIN_REV_SLEW_SHIFT	4
#define SC2705_VIN_REV_SLEW_MASK	(0x3 << 4)
#define SC2705_VSYS_SLEW_SHIFT		6
#define SC2705_VSYS_SLEW_MASK		(0x3 << 6)

/* SC2705_DCDC_CTRL_F = 0x22 */
#define SC2705_DCDC_REV_VOUT_SHIFT	0
#define SC2705_DCDC_REV_VOUT_MASK	(0xF << 0)
#define SC2705_CHG_RESTART_SHIFT	7
#define SC2705_CHG_RESTART_MASK		BIT(7)

/* SC2705_CHG_CTRL_A = 0x23 */
#define SC2705_VBAT_CHG_SHIFT		0
#define SC2705_VBAT_CHG_MASK		(0x3F << 0)
#define SC2705_VBAT_RECHG_SHIFT		6
#define SC2705_VBAT_RECHG_MASK		(0x3 << 6)

/* SC2705_CHG_CTRL_B = 0x24 */
#define SC2705_IBAT_CHG_SHIFT		0
#define SC2705_IBAT_CHG_MASK		(0x7F << 0)
#define SC2705_IBAT_CC1_EN_SHIFT	7
#define SC2705_IBAT_CC1_EN_MASK		BIT(7)

/* SC2705_CHG_CTRL_C = 0x25 */
#define SC2705_VSYS_MIN_SHIFT		0
#define SC2705_VSYS_MIN_MASK		(0xF << 0)
#define SC2705_IBAT_CHG_SLEW_SHIFT	4
#define SC2705_IBAT_CHG_SLEW_MASK	(0x3 << 4)

/* SC2705_CHG_CTRL_D = 0x26 */
#define SC2705_IBAT_PRE_SHIFT		0
#define SC2705_IBAT_PRE_MASK		(0x3 << 0)
#define SC2705_IBAT_TERM_SHIFT		2
#define SC2705_IBAT_TERM_MASK		(0x7 << 2)
#define SC2705_T_EOC_SHIFT		5
#define SC2705_T_EOC_MASK		(0x7 << 5)

/* SC2705_CHG_CTRL_E = 0x27 */
#define SC2705_IBAT_COLD_SHIFT		0
#define SC2705_IBAT_COLD_MASK		 BIT(0)
#define SC2705_IBAT_WARM_SHIFT		1
#define SC2705_IBAT_WARM_MASK		 BIT(1)
#define SC2705_VBAT_COLD_SHIFT		2
#define SC2705_VBAT_COLD_MASK		 (0x3 << 2)
#define SC2705_VBAT_WARM_SHIFT		4
#define SC2705_VBAT_WARM_MASK		 (0x3 << 4)
#define SC2705_CHG_STAT_EVENT_SEL_SHIFT       6
#define SC2705_CHG_STAT_EVENT_SEL_MASK	(0x3 << 6)

/* SC2705_BATSW_CTRL_A = 0x28 */
#define SC2705_BAT_ISO_LONG_SHIFT	0
#define SC2705_BAT_ISO_LONG_MASK	BIT(0)
#define SC2705_BAT_ISO_SHORT_SHIFT	1
#define SC2705_BAT_ISO_SHORT_MASK	BIT(1)
#define SC2705_BAT_ISO_FULL_SHIFT	2
#define SC2705_BAT_ISO_FULL_MASK	BIT(2)
#define SC2705_BAT_ISO_GPI_SHIFT	3
#define SC2705_BAT_ISO_GPI_MASK		BIT(3)
#define SC2705_T_PRE_BAT_ISO_SHIFT	4
#define SC2705_T_PRE_BAT_ISO_MASK	(0x3 << 4)

/* SC2705_TBAT_CTRL_A = 0x29 */
#define SC2705_TBAT_T3_SHIFT		0
#define SC2705_TBAT_T3_MASK		(0x3 << 0)
#define SC2705_TBAT_T4_SHIFT		2
#define SC2705_TBAT_T4_MASK		(0x3 << 2)
#define SC2705_TBAT_L2_EN_SHIFT		4
#define SC2705_TBAT_L2_EN_MASK		BIT(4)
#define SC2705_TBAT_AUTO_SHIFT		5
#define SC2705_TBAT_AUTO_MASK		BIT(5)
#define SC2705_TBAT_EXT_SHIFT		6
#define SC2705_TBAT_EXT_MASK		BIT(6)

/* SC2705_TJUNC_CTRL_A = 0x2A */
#define SC2705_TJUNC_WARN_SHIFT		0
#define SC2705_TJUNC_WARN_MASK		(0x3 << 0)
#define SC2705_TJUNC_WARN_70C		(0x0 << 0)
#define SC2705_TJUNC_WARN_90C		(0x1 << 0)
#define SC2705_TJUNC_WARN_110C		(0x2 << 0)
#define SC2705_TJUNC_WARN_125C		(0x3 << 0)
#define SC2705_TJUNC_REG_SHIFT		2
#define SC2705_TJUNC_REG_MASK		BIT(2)

/* SC2705_ADC_CTRL_A = 0x2B */
#define SC2705_ADC_CNVRT_SHIFT		0
#define SC2705_ADC_CNVRT_MASK		BIT(0)

/* SC2705_ADC_RES_0 = 0x2C */
#define SC2705_ADC_RES_VIN_SHIFT	0
#define SC2705_ADC_RES_VIN_MASK		(0xFF << 0)

/* SC2705_ADC_RES_1 = 0x2D */
#define SC2705_ADC_RES_VBAT_SHIFT	0
#define SC2705_ADC_RES_VBAT_MASK	(0xFF << 0)

/* SC2705_ADC_RES_2 = 0x2E */
#define SC2705_ADC_RES_IIN_SHIFT	0
#define SC2705_ADC_RES_IIN_MASK		(0xFF << 0)

/* SC2705_ADC_RES_3 = 0x2F */
#define SC2705_ADC_RES_IBAT_SHIFT	0
#define SC2705_ADC_RES_IBAT_MASK	(0xFF << 0)

/* SC2705_ADC_RES_4 = 0x30 */
#define SC2705_ADC_RES_TJUNC_SHIFT	0
#define SC2705_ADC_RES_TJUNC_MASK	(0xFF << 0)

/* SC2705_ADC_RES_5 = 0x31 */
#define SC2705_ADC_RES_TBAT_SHIFT	0
#define SC2705_ADC_RES_TBAT_MASK	(0xFF << 0)

/* SC2705_GPIO_CONF_A = 0x32 */
#define SC2705_GPIO0_PIN_SHIFT		0
#define SC2705_GPIO0_PIN_MASK		(0x3 << 0)
#define SC2705_GPIO0_INT_EDGE_SHIFT	2
#define SC2705_GPIO0_INT_EDGE_MASK	BIT(2)
#define SC2705_GPIO0_OUT_SHIFT		3
#define SC2705_GPIO0_OUT_MASK		BIT(3)
#define SC2705_GPIO1_PIN_SHIFT		4
#define SC2705_GPIO1_PIN_MASK		(0x3 << 4)
#define SC2705_GPIO1_INT_EDGE_SHIFT	6
#define SC2705_GPIO1_INT_EDGE_MASK	BIT(6)
#define SC2705_GPIO1_OUT_SHIFT		7
#define SC2705_GPIO1_OUT_MASK		BIT(7)

/* SC2705_GPIO_CONF_A = 0x33 */
#define SC2705_GPIO2_PIN_SHIFT		0
#define SC2705_GPIO2_PIN_MASK		(0x3 << 0)
#define SC2705_GPIO2_INT_EDGE_SHIFT	2
#define SC2705_GPIO2_INT_EDGE_MASK	BIT(2)
#define SC2705_GPIO2_OUT_SHIFT		3
#define SC2705_GPIO2_OUT_MASK		BIT(3)
#define SC2705_GPIO3_PIN_SHIFT		4
#define SC2705_GPIO3_PIN_MASK		(0x3 << 4)
#define SC2705_GPIO3_INT_EDGE_SHIFT	6
#define SC2705_GPIO3_INT_EDGE_MASK	BIT(6)
#define SC2705_GPIO3_OUT_SHIFT		7
#define SC2705_GPIO3_OUT_MASK		BIT(7)

/* SC2705_TWI_CTRL_A = 0x34 */
#define SC2705_TWI_ADDR_SHIFT		1
#define SC2705_TWI_ADDR_MASK		(0x7F << 1)

/* SC2705_TWI_CTRL_B = 0x35 */
#define SC2705_TWI_TO_SHIFT		0
#define SC2705_TWI_TO_MASK		BIT(0)
#define SC2705_SDA_DEGLITCH_EN_SHIFT          1
#define SC2705_SDA_DEGLITCH_EN_MASK           BIT(1)
#define SC2705_SDA_DEGLITCH_HSPEED_SHIFT      2
#define SC2705_SDA_DEGLITCH_HSPEED_MASK       BIT(2)
#define SC2705_TWI_WR_MODE_SHIFT	3
#define SC2705_TWI_WR_MODE_MASK		BIT(3)
#define SC2705_SCL_DEGLITCH_EN_SHIFT          4
#define SC2705_SCL_DEGLITCH_EN_MASK           BIT(4)
#define SC2705_SCL_DEGLITCH_HSPEED_SHIFT      5
#define SC2705_SCL_DEGLITCH_HSPEED_MASK       BIT(5)
#define SC2705_SDA_EXTRA_THOLD_DELAY_SHIFT    6
#define SC2705_SDA_EXTRA_THOLD_DELAY_MASK     BIT(6)
#define SC2705_PP_EN_SHIFT		7
#define SC2705_PP_EN_MASK		BIT(7)


/* SC2705_CHG_TIMER_CTRL_A = 0x36 */
#define SC2705_TIMEOUT_CCCV_SHIFT	0
#define SC2705_TIMEOUT_CCCV_MASK	(0x7 << 0)
#define SC2705_TIMEOUT_PRE_SHIFT	4
#define SC2705_TIMEOUT_PRE_MASK		(0x3 << 4)
#define SC2705_CHG_TIMER_EN_SHIFT	7
#define SC2705_CHG_TIMER_EN_MASK	BIT(7)

/* SC2705_CHG_TIMER_CTRL_B = 0x37 */
#define SC2705_TIMER_LOAD_SHIFT		0
#define SC2705_TIMER_LOAD_MASK		(0xFF << 0)

/* SC2705_CHG_TIMER_CTRL_C = 0x38 */
#define SC2705_TIMER_COUNT_SHIFT	0
#define SC2705_TIMER_COUNT_MASK		(0xFF << 0)

/* SC2705_CONF_A = 0x40 */
#define SC2705_ONKEY_DET_EN_SHIFT	0
#define SC2705_ONKEY_DET_EN_MASK	BIT(0)
#define SC2705_WD_EN_SHIFT		1
#define SC2705_WD_EN_MASK		BIT(1)
#define SC2705_BAT_DET_SRC_SHIFT	2
#define SC2705_BAT_DET_SRC_MASK	(0x3 << 2)
#define SC2705_BAT_DET_CTRL_SHIFT	4
#define SC2705_BAT_DET_CTRL_MASK	BIT(4)
#define SC2705_ULP_WAKEUP_SRC_SEL_SHIFT	5
#define SC2705_ULP_WAKEUP_SRC_SEL_MASK	(0x3 << 5)
#define SC2705_ULP_EN_SHIFT		7
#define SC2705_ULP_EN_MASK		BIT(7)

/* SC2705_CONF_B = 0x41 */
#define SC2705_SPSP_TUNE_SHIFT		0
#define SC2705_SPSP_TUNE_MASK		(0x1F << 0)
#define SC2705_SPSP_TUNE_ENABLE_SHIFT	5
#define SC2705_SPSP_TUNE_ENABLE_MASK	BIT(5)
#define SC2705_SPSP_ENABLE_SHIFT	6
#define SC2705_SPSP_ENABLE_MASK	BIT(6)
#define SC2705_IDLE_LP_MODE_DIS_SHIFT	7
#define SC2705_IDLE_LP_MODE_DIS_MASK	BIT(7)

#endif /* __SC2705_REGISTERS_H */
